/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Uart_Ip_Reg.h                                                                             *
 *  \brief    This file contains interface header for UART MCAL driver.                                 *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2024/10/29     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

/* Generated by tool. Do not modify manually. */

#ifndef UART_IP_REG_H
#define UART_IP_REG_H

#ifdef __cplusplus
extern "C" {
#endif

#define UART_MCR0_OFF  0x0U

#define BM_MCR0_SELFTESTMODEEN  ((uint32)0x01U << 12U)

#define BM_MCR0_DEBUG_RX_FIFO_RD_EN  ((uint32)0x01U << 11U)

#define BM_MCR0_DEBUG_MODE_CTRL  ((uint32)0x01U << 10U)

#define BM_MCR0_DEBUG_MODE_SW_EN  ((uint32)0x01U << 9U)

#define BM_MCR0_QCHCTL  ((uint32)0x01U << 8U)

#define FM_MCR0_OPMOD  ((uint32)0xfU << 4U)
#define FV_MCR0_OPMOD(v) \
  (((uint32)(v) << 4U) & FM_MCR0_OPMOD)
#define GFV_MCR0_OPMOD(v) \
  (((uint32)(v) & FM_MCR0_OPMOD) >> 4U)

#define FM_MCR0_CGC  ((uint32)0x3U << 2U)
#define FV_MCR0_CGC(v) \
  (((uint32)(v) << 2U) & FM_MCR0_CGC)
#define GFV_MCR0_CGC(v) \
  (((uint32)(v) & FM_MCR0_CGC) >> 2U)

#define BM_MCR0_MODRST  ((uint32)0x01U << 1U)

#define BM_MCR0_MODEN  ((uint32)0x01U << 0U)

#define UART_PRDATAINJ_OFF  0x4U

#define BM_PRDATAINJ_B0  ((uint32)0x01U << 0U)

#define UART_MCR2_OFF  0x8U

#define FM_MCR2_PWDATAINJ  ((uint32)0xffffffffU << 0U)
#define FV_MCR2_PWDATAINJ(v) \
  (((uint32)(v) << 0U) & FM_MCR2_PWDATAINJ)
#define GFV_MCR2_PWDATAINJ(v) \
  (((uint32)(v) & FM_MCR2_PWDATAINJ) >> 0U)

#define UART_MCR3_OFF  0xcU

#define FM_MCR3_DMARXFWCODEINJ  ((uint32)0xfU << 28U)
#define FV_MCR3_DMARXFWCODEINJ(v) \
  (((uint32)(v) << 28U) & FM_MCR3_DMARXFWCODEINJ)
#define GFV_MCR3_DMARXFWCODEINJ(v) \
  (((uint32)(v) & FM_MCR3_DMARXFWCODEINJ) >> 28U)

#define FM_MCR3_DMARXFWDATAINJ  ((uint32)0x7U << 24U)
#define FV_MCR3_DMARXFWDATAINJ(v) \
  (((uint32)(v) << 24U) & FM_MCR3_DMARXFWDATAINJ)
#define GFV_MCR3_DMARXFWDATAINJ(v) \
  (((uint32)(v) & FM_MCR3_DMARXFWDATAINJ) >> 24U)

#define FM_MCR3_DMATXFWCODEINJ  ((uint32)0xfU << 20U)
#define FV_MCR3_DMATXFWCODEINJ(v) \
  (((uint32)(v) << 20U) & FM_MCR3_DMATXFWCODEINJ)
#define GFV_MCR3_DMATXFWCODEINJ(v) \
  (((uint32)(v) & FM_MCR3_DMATXFWCODEINJ) >> 20U)

#define FM_MCR3_DMATXFWDATAINJ  ((uint32)0x7U << 16U)
#define FV_MCR3_DMATXFWDATAINJ(v) \
  (((uint32)(v) << 16U) & FM_MCR3_DMATXFWDATAINJ)
#define GFV_MCR3_DMATXFWDATAINJ(v) \
  (((uint32)(v) & FM_MCR3_DMATXFWDATAINJ) >> 16U)

#define FM_MCR3_DMARXBWCODEINJ  ((uint32)0xfU << 12U)
#define FV_MCR3_DMARXBWCODEINJ(v) \
  (((uint32)(v) << 12U) & FM_MCR3_DMARXBWCODEINJ)
#define GFV_MCR3_DMARXBWCODEINJ(v) \
  (((uint32)(v) & FM_MCR3_DMARXBWCODEINJ) >> 12U)

#define FM_MCR3_DMARXBWDATAINJ  ((uint32)0xfU << 8U)
#define FV_MCR3_DMARXBWDATAINJ(v) \
  (((uint32)(v) << 8U) & FM_MCR3_DMARXBWDATAINJ)
#define GFV_MCR3_DMARXBWDATAINJ(v) \
  (((uint32)(v) & FM_MCR3_DMARXBWDATAINJ) >> 8U)

#define FM_MCR3_DMATXBWCODEINJ  ((uint32)0xfU << 4U)
#define FV_MCR3_DMATXBWCODEINJ(v) \
  (((uint32)(v) << 4U) & FM_MCR3_DMATXBWCODEINJ)
#define GFV_MCR3_DMATXBWCODEINJ(v) \
  (((uint32)(v) & FM_MCR3_DMATXBWCODEINJ) >> 4U)

#define FM_MCR3_DMATXBWDATAINJ  ((uint32)0xfU << 0U)
#define FV_MCR3_DMATXBWDATAINJ(v) \
  (((uint32)(v) << 0U) & FM_MCR3_DMATXBWDATAINJ)
#define GFV_MCR3_DMATXBWDATAINJ(v) \
  (((uint32)(v) & FM_MCR3_DMATXBWDATAINJ) >> 0U)

#define UART_MCR4_OFF  0x10U

#define BM_MCR4_ERRINJINTERRUPTERRUNCORR  ((uint32)0x01U << 9U)

#define BM_MCR4_ERRINJINTERRUPTERRCORR  ((uint32)0x01U << 8U)

#define BM_MCR4_ERRINJINTERRUPT  ((uint32)0x01U << 7U)

#define FM_MCR4_PWECCINJ  ((uint32)0x7fU << 0U)
#define FV_MCR4_PWECCINJ(v) \
  (((uint32)(v) << 0U) & FM_MCR4_PWECCINJ)
#define GFV_MCR4_PWECCINJ(v) \
  (((uint32)(v) & FM_MCR4_PWECCINJ) >> 0U)

#define UART_MSR0_OFF  0x18U

#define FM_MSR0_SCR_STATE  ((uint32)0x1ffU << 6U)
#define FV_MSR0_SCR_STATE(v) \
  (((uint32)(v) << 6U) & FM_MSR0_SCR_STATE)
#define GFV_MSR0_SCR_STATE(v) \
  (((uint32)(v) & FM_MSR0_SCR_STATE) >> 6U)

#define FM_MSR0_PCR_STATE  ((uint32)0x3fU << 0U)
#define FV_MSR0_PCR_STATE(v) \
  (((uint32)(v) << 0U) & FM_MSR0_PCR_STATE)
#define GFV_MSR0_PCR_STATE(v) \
  (((uint32)(v) & FM_MSR0_PCR_STATE) >> 0U)

#define UART_INTR0_OFF  0x20U

#define BM_INTR0_IO3EDGE  ((uint32)0x01U << 31U)

#define BM_INTR0_IO2EDGE  ((uint32)0x01U << 30U)

#define BM_INTR0_IO1EDGE  ((uint32)0x01U << 29U)

#define BM_INTR0_IO0EDGE  ((uint32)0x01U << 28U)

#define BM_INTR0_LINBUSSTUCK  ((uint32)0x01U << 27U)

#define BM_INTR0_RXCHKSUMERR  ((uint32)0x01U << 26U)

#define BM_INTR0_RXCHKSUMPASS  ((uint32)0x01U << 25U)

#define BM_INTR0_RXPIDERR  ((uint32)0x01U << 24U)

#define BM_INTR0_RXPIDPASS  ((uint32)0x01U << 23U)

#define BM_INTR0_APBCMDABORT  ((uint32)0x01U << 22U)

#define BM_INTR0_APBCMDDONE  ((uint32)0x01U << 21U)

#define BM_INTR0_STARTERR  ((uint32)0x01U << 20U)

#define BM_INTR0_ABRFAIL  ((uint32)0x01U << 19U)

#define BM_INTR0_ABRPASS  ((uint32)0x01U << 18U)

#define BM_INTR0_TC  ((uint32)0x01U << 17U)

#define BM_INTR0_CHARMATCH  ((uint32)0x01U << 16U)

#define BM_INTR0_RXADDR  ((uint32)0x01U << 15U)

#define BM_INTR0_RXIDLE  ((uint32)0x01U << 14U)

#define BM_INTR0_RXBREAK  ((uint32)0x01U << 13U)

#define BM_INTR0_RXTO  ((uint32)0x01U << 12U)

#define BM_INTR0_NOISEERR  ((uint32)0x01U << 11U)

#define BM_INTR0_BAUDRATEERR  ((uint32)0x01U << 10U)

#define BM_INTR0_FRAMEERR  ((uint32)0x01U << 9U)

#define BM_INTR0_PARITYERR  ((uint32)0x01U << 8U)

#define BM_INTR0_RXFABT  ((uint32)0x01U << 7U)

#define BM_INTR0_TXFABT  ((uint32)0x01U << 6U)

#define BM_INTR0_RXFOVF  ((uint32)0x01U << 5U)

#define BM_INTR0_TXFOVF  ((uint32)0x01U << 4U)

#define BM_INTR0_RXFUDF  ((uint32)0x01U << 3U)

#define BM_INTR0_TXFUDF  ((uint32)0x01U << 2U)

#define BM_INTR0_RXFWF  ((uint32)0x01U << 1U)

#define BM_INTR0_TXFWE  ((uint32)0x01U << 0U)

#define UART_INTR3_OFF  0x2cU

#define BM_INTR3_DEBUGMODEERR  ((uint32)0x01U << 27U)

#define BM_INTR3_REGPAREJENERR  ((uint32)0x01U << 26U)

#define BM_INTR3_SELFTESTMODEERR  ((uint32)0x01U << 25U)

#define BM_INTR3_PWDATAFATAL  ((uint32)0x01U << 22U)

#define BM_INTR3_PWDATAUNCERR  ((uint32)0x01U << 21U)

#define BM_INTR3_PWDATACORERR  ((uint32)0x01U << 20U)

#define BM_INTR3_PADDRUNCERR  ((uint32)0x01U << 19U)

#define BM_INTR3_PUSERUNCERR  ((uint32)0x01U << 18U)

#define BM_INTR3_PCTL1UNCERR  ((uint32)0x01U << 17U)

#define BM_INTR3_PCTL0UNCERR  ((uint32)0x01U << 16U)

#define BM_INTR3_DMARXBWFATALERR  ((uint32)0x01U << 12U)

#define BM_INTR3_DMARXBWCORRERR  ((uint32)0x01U << 11U)

#define BM_INTR3_DMARXBWUNCORRERR  ((uint32)0x01U << 10U)

#define BM_INTR3_DMARXEOBCERR  ((uint32)0x01U << 9U)

#define BM_INTR3_DMARXEOBAERR  ((uint32)0x01U << 8U)

#define BM_INTR3_DMATXBWFATALERR  ((uint32)0x01U << 4U)

#define BM_INTR3_DMATXBWCORRERR  ((uint32)0x01U << 3U)

#define BM_INTR3_DMATXBWUNCORRERR  ((uint32)0x01U << 2U)

#define BM_INTR3_DMATXEOBCERR  ((uint32)0x01U << 1U)

#define BM_INTR3_DMATXEOBAERR  ((uint32)0x01U << 0U)

#define UART_INTEN0_OFF  0x30U

#define BM_INTEN0_IO3EDGEE  ((uint32)0x01U << 31U)

#define BM_INTEN0_IO2EDGEE  ((uint32)0x01U << 30U)

#define BM_INTEN0_IO1EDGEE  ((uint32)0x01U << 29U)

#define BM_INTEN0_IO0EDGEE  ((uint32)0x01U << 28U)

#define BM_INTEN0_LINBUSSTUCKE  ((uint32)0x01U << 27U)

#define BM_INTEN0_RXCHKSUMERRE  ((uint32)0x01U << 26U)

#define BM_INTEN0_RXCHKSUMPASSE  ((uint32)0x01U << 25U)

#define BM_INTEN0_RXPIDERRE  ((uint32)0x01U << 24U)

#define BM_INTEN0_RXPIDPASSE  ((uint32)0x01U << 23U)

#define BM_INTEN0_APBCMDABORTE  ((uint32)0x01U << 22U)

#define BM_INTEN0_APBCMDDONEE  ((uint32)0x01U << 21U)

#define BM_INTEN0_STARTERRE  ((uint32)0x01U << 20U)

#define BM_INTEN0_ABRFAILE  ((uint32)0x01U << 19U)

#define BM_INTEN0_ABRPASSE  ((uint32)0x01U << 18U)

#define BM_INTEN0_TCE  ((uint32)0x01U << 17U)

#define BM_INTEN0_CHARMATCHE  ((uint32)0x01U << 16U)

#define BM_INTEN0_RXADDRE  ((uint32)0x01U << 15U)

#define BM_INTEN0_RXIDLEE  ((uint32)0x01U << 14U)

#define BM_INTEN0_RXBREAKE  ((uint32)0x01U << 13U)

#define BM_INTEN0_RXTOE  ((uint32)0x01U << 12U)

#define BM_INTEN0_NOISEERRE  ((uint32)0x01U << 11U)

#define BM_INTEN0_BAUDRATEERRE  ((uint32)0x01U << 10U)

#define BM_INTEN0_FRAMEERRE  ((uint32)0x01U << 9U)

#define BM_INTEN0_PARITYERRE  ((uint32)0x01U << 8U)

#define BM_INTEN0_RXFABTE  ((uint32)0x01U << 7U)

#define BM_INTEN0_TXFABTE  ((uint32)0x01U << 6U)

#define BM_INTEN0_RXFOVFE  ((uint32)0x01U << 5U)

#define BM_INTEN0_TXFOVFE  ((uint32)0x01U << 4U)

#define BM_INTEN0_RXFUDFE  ((uint32)0x01U << 3U)

#define BM_INTEN0_TXFUDFE  ((uint32)0x01U << 2U)

#define BM_INTEN0_RXFWFE  ((uint32)0x01U << 1U)

#define BM_INTEN0_TXFWEE  ((uint32)0x01U << 0U)

#define UART_INTEN3_OFF  0x3cU

#define BM_INTEN3_DEBUGMODEERRE  ((uint32)0x01U << 27U)

#define BM_INTEN3_REGPAREJENERRE  ((uint32)0x01U << 26U)

#define BM_INTEN3_SELFTESTMODEERRE  ((uint32)0x01U << 25U)

#define BM_INTEN3_PWDATAFATALE  ((uint32)0x01U << 22U)

#define BM_INTEN3_PWDATAUNCERRE  ((uint32)0x01U << 21U)

#define BM_INTEN3_PWDATACORERRE  ((uint32)0x01U << 20U)

#define BM_INTEN3_PADDRUNCERRE  ((uint32)0x01U << 19U)

#define BM_INTEN3_PUSERUNCERRE  ((uint32)0x01U << 18U)

#define BM_INTEN3_PCTL1UNCERRE  ((uint32)0x01U << 17U)

#define BM_INTEN3_PCTL0UNCERRE  ((uint32)0x01U << 16U)

#define BM_INTEN3_DMARXBWFATALERRE  ((uint32)0x01U << 12U)

#define BM_INTEN3_DMARXBWCORRERRE  ((uint32)0x01U << 11U)

#define BM_INTEN3_DMARXBWUNCORRERRE  ((uint32)0x01U << 10U)

#define BM_INTEN3_DMARXEOBCERRE  ((uint32)0x01U << 9U)

#define BM_INTEN3_DMARXEOBAERRE  ((uint32)0x01U << 8U)

#define BM_INTEN3_DMATXBWFATALERRE  ((uint32)0x01U << 4U)

#define BM_INTEN3_DMATXBWCORRERRE  ((uint32)0x01U << 3U)

#define BM_INTEN3_DMATXBWUNCORRERRE  ((uint32)0x01U << 2U)

#define BM_INTEN3_DMATXEOBCERRE  ((uint32)0x01U << 1U)

#define BM_INTEN3_DMATXEOBAERRE  ((uint32)0x01U << 0U)

#define UART_CMDCSR0_OFF  0x40U

#define FM_CMDCSR0_DOORBELL  ((uint32)0xffffU << 0U)
#define FV_CMDCSR0_DOORBELL(v) \
  (((uint32)(v) << 0U) & FM_CMDCSR0_DOORBELL)
#define GFV_CMDCSR0_DOORBELL(v) \
  (((uint32)(v) & FM_CMDCSR0_DOORBELL) >> 0U)

#define UART_CMDCSR1_OFF  0x44U

#define FM_CMDCSR1_PID  ((uint32)0xffU << 16U)
#define FV_CMDCSR1_PID(v) \
  (((uint32)(v) << 16U) & FM_CMDCSR1_PID)
#define GFV_CMDCSR1_PID(v) \
  (((uint32)(v) & FM_CMDCSR1_PID) >> 16U)

#define FM_CMDCSR1_RXBYTENUM  ((uint32)0xffU << 8U)
#define FV_CMDCSR1_RXBYTENUM(v) \
  (((uint32)(v) << 8U) & FM_CMDCSR1_RXBYTENUM)
#define GFV_CMDCSR1_RXBYTENUM(v) \
  (((uint32)(v) & FM_CMDCSR1_RXBYTENUM) >> 8U)

#define FM_CMDCSR1_TXBYTENUM  ((uint32)0xffU << 0U)
#define FV_CMDCSR1_TXBYTENUM(v) \
  (((uint32)(v) << 0U) & FM_CMDCSR1_TXBYTENUM)
#define GFV_CMDCSR1_TXBYTENUM(v) \
  (((uint32)(v) & FM_CMDCSR1_TXBYTENUM) >> 0U)

#define UART_FCR0_OFF  0x50U

#define BM_FCR0_CLRTXF  ((uint32)0x01U << 16U)

#define FM_FCR0_TXWMLVL  ((uint32)0xffU << 0U)
#define FV_FCR0_TXWMLVL(v) \
  (((uint32)(v) << 0U) & FM_FCR0_TXWMLVL)
#define GFV_FCR0_TXWMLVL(v) \
  (((uint32)(v) & FM_FCR0_TXWMLVL) >> 0U)

#define UART_FCR1_OFF  0x54U

#define BM_FCR1_CLRRXF  ((uint32)0x01U << 16U)

#define FM_FCR1_RXWMLVL  ((uint32)0xffU << 0U)
#define FV_FCR1_RXWMLVL(v) \
  (((uint32)(v) << 0U) & FM_FCR1_RXWMLVL)
#define GFV_FCR1_RXWMLVL(v) \
  (((uint32)(v) & FM_FCR1_RXWMLVL) >> 0U)

#define UART_FSR0_OFF  0x60U

#define BM_FSR0_FULL  ((uint32)0x01U << 25U)

#define BM_FSR0_EMPTY  ((uint32)0x01U << 24U)

#define FM_FSR0_FIFOSZ  ((uint32)0xffU << 16U)
#define FV_FSR0_FIFOSZ(v) \
  (((uint32)(v) << 16U) & FM_FSR0_FIFOSZ)
#define GFV_FSR0_FIFOSZ(v) \
  (((uint32)(v) & FM_FSR0_FIFOSZ) >> 16U)

#define FM_FSR0_EMPTYLVL  ((uint32)0xffU << 8U)
#define FV_FSR0_EMPTYLVL(v) \
  (((uint32)(v) << 8U) & FM_FSR0_EMPTYLVL)
#define GFV_FSR0_EMPTYLVL(v) \
  (((uint32)(v) & FM_FSR0_EMPTYLVL) >> 8U)

#define FM_FSR0_FILLLVL  ((uint32)0xffU << 0U)
#define FV_FSR0_FILLLVL(v) \
  (((uint32)(v) << 0U) & FM_FSR0_FILLLVL)
#define GFV_FSR0_FILLLVL(v) \
  (((uint32)(v) & FM_FSR0_FILLLVL) >> 0U)

#define UART_FSR1_OFF  0x64U

#define BM_FSR1_FULL  ((uint32)0x01U << 25U)

#define BM_FSR1_EMPTY  ((uint32)0x01U << 24U)

#define FM_FSR1_FIFOSZ  ((uint32)0xffU << 16U)
#define FV_FSR1_FIFOSZ(v) \
  (((uint32)(v) << 16U) & FM_FSR1_FIFOSZ)
#define GFV_FSR1_FIFOSZ(v) \
  (((uint32)(v) & FM_FSR1_FIFOSZ) >> 16U)

#define FM_FSR1_EMPTYLVL  ((uint32)0xffU << 8U)
#define FV_FSR1_EMPTYLVL(v) \
  (((uint32)(v) << 8U) & FM_FSR1_EMPTYLVL)
#define GFV_FSR1_EMPTYLVL(v) \
  (((uint32)(v) & FM_FSR1_EMPTYLVL) >> 8U)

#define FM_FSR1_FILLLVL  ((uint32)0xffU << 0U)
#define FV_FSR1_FILLLVL(v) \
  (((uint32)(v) << 0U) & FM_FSR1_FILLLVL)
#define GFV_FSR1_FILLLVL(v) \
  (((uint32)(v) & FM_FSR1_FILLLVL) >> 0U)

#define UART_DMACR_OFF  0x70U

#define BM_DMACR_RXDMARST  ((uint32)0x01U << 3U)

#define BM_DMACR_TXDMARST  ((uint32)0x01U << 2U)

#define BM_DMACR_RXDMAE  ((uint32)0x01U << 1U)

#define BM_DMACR_TXDMAE  ((uint32)0x01U << 0U)

#define UART_DMASR_OFF  0x74U

#define BM_DMASR_RXDMAREQ  ((uint32)0x01U << 5U)

#define BM_DMASR_TXDMAREQ  ((uint32)0x01U << 4U)

#define FM_DMASR_RXDMA_STATE  ((uint32)0x3U << 2U)
#define FV_DMASR_RXDMA_STATE(v) \
  (((uint32)(v) << 2U) & FM_DMASR_RXDMA_STATE)
#define GFV_DMASR_RXDMA_STATE(v) \
  (((uint32)(v) & FM_DMASR_RXDMA_STATE) >> 2U)

#define FM_DMASR_TXDMA_STATE  ((uint32)0x3U << 0U)
#define FV_DMASR_TXDMA_STATE(v) \
  (((uint32)(v) << 0U) & FM_DMASR_TXDMA_STATE)
#define GFV_DMASR_TXDMA_STATE(v) \
  (((uint32)(v) & FM_DMASR_TXDMA_STATE) >> 0U)

#define UART_PCR0_OFF  0x80U

#define FM_PCR0_RXMUTECTL  ((uint32)0x3U << 29U)
#define FV_PCR0_RXMUTECTL(v) \
  (((uint32)(v) << 29U) & FM_PCR0_RXMUTECTL)
#define GFV_PCR0_RXMUTECTL(v) \
  (((uint32)(v) & FM_PCR0_RXMUTECTL) >> 29U)

#define BM_PCR0_TRANSFERMODE  ((uint32)0x01U << 28U)

#define FM_PCR0_FCM  ((uint32)0x7U << 25U)
#define FV_PCR0_FCM(v) \
  (((uint32)(v) << 25U) & FM_PCR0_FCM)
#define GFV_PCR0_FCM(v) \
  (((uint32)(v) & FM_PCR0_FCM) >> 25U)

#define FM_PCR0_ABRCTL1  ((uint32)0x7U << 22U)
#define FV_PCR0_ABRCTL1(v) \
  (((uint32)(v) << 22U) & FM_PCR0_ABRCTL1)
#define GFV_PCR0_ABRCTL1(v) \
  (((uint32)(v) & FM_PCR0_ABRCTL1) >> 22U)

#define FM_PCR0_ABRCTL0  ((uint32)0xfU << 18U)
#define FV_PCR0_ABRCTL0(v) \
  (((uint32)(v) << 18U) & FM_PCR0_ABRCTL0)
#define GFV_PCR0_ABRCTL0(v) \
  (((uint32)(v) & FM_PCR0_ABRCTL0) >> 18U)

#define BM_PCR0_ABREN  ((uint32)0x01U << 17U)

#define BM_PCR0_ADDRBIT  ((uint32)0x01U << 16U)

#define FM_PCR0_PARITYBIT  ((uint32)0x7U << 13U)
#define FV_PCR0_PARITYBIT(v) \
  (((uint32)(v) << 13U) & FM_PCR0_PARITYBIT)
#define GFV_PCR0_PARITYBIT(v) \
  (((uint32)(v) & FM_PCR0_PARITYBIT) >> 13U)

#define FM_PCR0_STOPBIT  ((uint32)0x3U << 11U)
#define FV_PCR0_STOPBIT(v) \
  (((uint32)(v) << 11U) & FM_PCR0_STOPBIT)
#define GFV_PCR0_STOPBIT(v) \
  (((uint32)(v) & FM_PCR0_STOPBIT) >> 11U)

#define FM_PCR0_DATABIT  ((uint32)0x7U << 8U)
#define FV_PCR0_DATABIT(v) \
  (((uint32)(v) << 8U) & FM_PCR0_DATABIT)
#define GFV_PCR0_DATABIT(v) \
  (((uint32)(v) & FM_PCR0_DATABIT) >> 8U)

#define BM_PCR0_BITORDER  ((uint32)0x01U << 7U)

#define BM_PCR0_RXEN  ((uint32)0x01U << 6U)

#define BM_PCR0_TXEN  ((uint32)0x01U << 5U)

#define FM_PCR0_PRESCALE  ((uint32)0x1fU << 0U)
#define FV_PCR0_PRESCALE(v) \
  (((uint32)(v) << 0U) & FM_PCR0_PRESCALE)
#define GFV_PCR0_PRESCALE(v) \
  (((uint32)(v) & FM_PCR0_PRESCALE) >> 0U)

#define UART_PCR1_OFF  0x84U

#define FM_PCR1_RXIDLECTL  ((uint32)0x7U << 29U)
#define FV_PCR1_RXIDLECTL(v) \
  (((uint32)(v) << 29U) & FM_PCR1_RXIDLECTL)
#define GFV_PCR1_RXIDLECTL(v) \
  (((uint32)(v) & FM_PCR1_RXIDLECTL) >> 29U)

#define FM_PCR1_RXBREAKCTL  ((uint32)0x7U << 26U)
#define FV_PCR1_RXBREAKCTL(v) \
  (((uint32)(v) << 26U) & FM_PCR1_RXBREAKCTL)
#define GFV_PCR1_RXBREAKCTL(v) \
  (((uint32)(v) & FM_PCR1_RXBREAKCTL) >> 26U)

#define FM_PCR1_SAMPLERATE  ((uint32)0x3U << 24U)
#define FV_PCR1_SAMPLERATE(v) \
  (((uint32)(v) << 24U) & FM_PCR1_SAMPLERATE)
#define GFV_PCR1_SAMPLERATE(v) \
  (((uint32)(v) & FM_PCR1_SAMPLERATE) >> 24U)

#define FM_PCR1_BAUDRATECNT  ((uint32)0xffffffU << 0U)
#define FV_PCR1_BAUDRATECNT(v) \
  (((uint32)(v) << 0U) & FM_PCR1_BAUDRATECNT)
#define GFV_PCR1_BAUDRATECNT(v) \
  (((uint32)(v) & FM_PCR1_BAUDRATECNT) >> 0U)

#define UART_PCR2_OFF  0x88U

#define FM_PCR2_ADDRMSK  ((uint32)0xffU << 24U)
#define FV_PCR2_ADDRMSK(v) \
  (((uint32)(v) << 24U) & FM_PCR2_ADDRMSK)
#define GFV_PCR2_ADDRMSK(v) \
  (((uint32)(v) & FM_PCR2_ADDRMSK) >> 24U)

#define FM_PCR2_ADDRCHAR  ((uint32)0xffU << 16U)
#define FV_PCR2_ADDRCHAR(v) \
  (((uint32)(v) << 16U) & FM_PCR2_ADDRCHAR)
#define GFV_PCR2_ADDRCHAR(v) \
  (((uint32)(v) & FM_PCR2_ADDRCHAR) >> 16U)

#define FM_PCR2_CHAR2  ((uint32)0xffU << 8U)
#define FV_PCR2_CHAR2(v) \
  (((uint32)(v) << 8U) & FM_PCR2_CHAR2)
#define GFV_PCR2_CHAR2(v) \
  (((uint32)(v) & FM_PCR2_CHAR2) >> 8U)

#define FM_PCR2_CHAR1  ((uint32)0xffU << 0U)
#define FV_PCR2_CHAR1(v) \
  (((uint32)(v) << 0U) & FM_PCR2_CHAR1)
#define GFV_PCR2_CHAR1(v) \
  (((uint32)(v) & FM_PCR2_CHAR1) >> 0U)

#define UART_PCR3_OFF  0x8cU

#define FM_PCR3_DEDT  ((uint32)0xffU << 24U)
#define FV_PCR3_DEDT(v) \
  (((uint32)(v) << 24U) & FM_PCR3_DEDT)
#define GFV_PCR3_DEDT(v) \
  (((uint32)(v) & FM_PCR3_DEDT) >> 24U)

#define FM_PCR3_DEAT  ((uint32)0xffU << 16U)
#define FV_PCR3_DEAT(v) \
  (((uint32)(v) << 16U) & FM_PCR3_DEAT)
#define GFV_PCR3_DEAT(v) \
  (((uint32)(v) & FM_PCR3_DEAT) >> 16U)

#define FM_PCR3_RE2DE  ((uint32)0xffU << 8U)
#define FV_PCR3_RE2DE(v) \
  (((uint32)(v) << 8U) & FM_PCR3_RE2DE)
#define GFV_PCR3_RE2DE(v) \
  (((uint32)(v) & FM_PCR3_RE2DE) >> 8U)

#define FM_PCR3_DE2RE  ((uint32)0xffU << 0U)
#define FV_PCR3_DE2RE(v) \
  (((uint32)(v) << 0U) & FM_PCR3_DE2RE)
#define GFV_PCR3_DE2RE(v) \
  (((uint32)(v) & FM_PCR3_DE2RE) >> 0U)

#define UART_PCR4_OFF  0x90U

#define FM_PCR4_RXTOCTL  ((uint32)0x7U << 20U)
#define FV_PCR4_RXTOCTL(v) \
  (((uint32)(v) << 20U) & FM_PCR4_RXTOCTL)
#define GFV_PCR4_RXTOCTL(v) \
  (((uint32)(v) & FM_PCR4_RXTOCTL) >> 20U)

#define BM_PCR4_BCLKOE  ((uint32)0x01U << 19U)

#define FM_PCR4_CHARMATCHCTL  ((uint32)0x7U << 16U)
#define FV_PCR4_CHARMATCHCTL(v) \
  (((uint32)(v) << 16U) & FM_PCR4_CHARMATCHCTL)
#define GFV_PCR4_CHARMATCHCTL(v) \
  (((uint32)(v) & FM_PCR4_CHARMATCHCTL) >> 16U)

#define FM_PCR4_TXIDLECTL  ((uint32)0xfU << 12U)
#define FV_PCR4_TXIDLECTL(v) \
  (((uint32)(v) << 12U) & FM_PCR4_TXIDLECTL)
#define GFV_PCR4_TXIDLECTL(v) \
  (((uint32)(v) & FM_PCR4_TXIDLECTL) >> 12U)

#define FM_PCR4_TXBREAKCTL  ((uint32)0xfU << 8U)
#define FV_PCR4_TXBREAKCTL(v) \
  (((uint32)(v) << 8U) & FM_PCR4_TXBREAKCTL)
#define GFV_PCR4_TXBREAKCTL(v) \
  (((uint32)(v) & FM_PCR4_TXBREAKCTL) >> 8U)

#define BM_PCR4_TXIDLE  ((uint32)0x01U << 2U)

#define BM_PCR4_TXBREAK  ((uint32)0x01U << 1U)

#define BM_PCR4_TXADDR  ((uint32)0x01U << 0U)

#define UART_PCR5_OFF  0x94U

#define FM_PCR5_SIRRXPUL  ((uint32)0xffU << 24U)
#define FV_PCR5_SIRRXPUL(v) \
  (((uint32)(v) << 24U) & FM_PCR5_SIRRXPUL)
#define GFV_PCR5_SIRRXPUL(v) \
  (((uint32)(v) & FM_PCR5_SIRRXPUL) >> 24U)

#define FM_PCR5_SIRTXPUL  ((uint32)0xffU << 16U)
#define FV_PCR5_SIRTXPUL(v) \
  (((uint32)(v) << 16U) & FM_PCR5_SIRTXPUL)
#define GFV_PCR5_SIRTXPUL(v) \
  (((uint32)(v) & FM_PCR5_SIRTXPUL) >> 16U)

#define FM_PCR5_TXCHARINT  ((uint32)0xffU << 0U)
#define FV_PCR5_TXCHARINT(v) \
  (((uint32)(v) << 0U) & FM_PCR5_TXCHARINT)
#define GFV_PCR5_TXCHARINT(v) \
  (((uint32)(v) & FM_PCR5_TXCHARINT) >> 0U)

#define UART_PCR6_OFF  0x98U

#define BM_PCR6_CHKSUMTYP  ((uint32)0x01U << 3U)

#define FM_PCR6_LINBREAKDEL  ((uint32)0x7U << 0U)
#define FV_PCR6_LINBREAKDEL(v) \
  (((uint32)(v) << 0U) & FM_PCR6_LINBREAKDEL)
#define GFV_PCR6_LINBREAKDEL(v) \
  (((uint32)(v) & FM_PCR6_LINBREAKDEL) >> 0U)

#define UART_PCR7_OFF  0x9cU

#define FM_PCR7_PCMDTOVAL  ((uint32)0xfU << 4U)
#define FV_PCR7_PCMDTOVAL(v) \
  (((uint32)(v) << 4U) & FM_PCR7_PCMDTOVAL)
#define GFV_PCR7_PCMDTOVAL(v) \
  (((uint32)(v) & FM_PCR7_PCMDTOVAL) >> 4U)

#define FM_PCR7_PCMDTOUNIT  ((uint32)0xfU << 0U)
#define FV_PCR7_PCMDTOUNIT(v) \
  (((uint32)(v) << 0U) & FM_PCR7_PCMDTOUNIT)
#define GFV_PCR7_PCMDTOUNIT(v) \
  (((uint32)(v) & FM_PCR7_PCMDTOUNIT) >> 0U)

#define UART_PCR8_OFF  0xa0U

#define FM_PCR8_RXFILTCTL  ((uint32)0x7U << 18U)
#define FV_PCR8_RXFILTCTL(v) \
  (((uint32)(v) << 18U) & FM_PCR8_RXFILTCTL)
#define GFV_PCR8_RXFILTCTL(v) \
  (((uint32)(v) & FM_PCR8_RXFILTCTL) >> 18U)

#define BM_PCR8_RXSYNCEN  ((uint32)0x01U << 17U)

#define BM_PCR8_RXPOL  ((uint32)0x01U << 16U)

#define FM_PCR8_RXEDGESEL  ((uint32)0x3U << 14U)
#define FV_PCR8_RXEDGESEL(v) \
  (((uint32)(v) << 14U) & FM_PCR8_RXEDGESEL)
#define GFV_PCR8_RXEDGESEL(v) \
  (((uint32)(v) & FM_PCR8_RXEDGESEL) >> 14U)

#define FM_PCR8_RXMODE  ((uint32)0x3U << 12U)
#define FV_PCR8_RXMODE(v) \
  (((uint32)(v) << 12U) & FM_PCR8_RXMODE)
#define GFV_PCR8_RXMODE(v) \
  (((uint32)(v) & FM_PCR8_RXMODE) >> 12U)

#define FM_PCR8_RXSEL  ((uint32)0xfU << 8U)
#define FV_PCR8_RXSEL(v) \
  (((uint32)(v) << 8U) & FM_PCR8_RXSEL)
#define GFV_PCR8_RXSEL(v) \
  (((uint32)(v) & FM_PCR8_RXSEL) >> 8U)

#define BM_PCR8_TXPOL  ((uint32)0x01U << 7U)

#define FM_PCR8_TXMODE  ((uint32)0x7U << 4U)
#define FV_PCR8_TXMODE(v) \
  (((uint32)(v) << 4U) & FM_PCR8_TXMODE)
#define GFV_PCR8_TXMODE(v) \
  (((uint32)(v) & FM_PCR8_TXMODE) >> 4U)

#define FM_PCR8_TXSEL  ((uint32)0xfU << 0U)
#define FV_PCR8_TXSEL(v) \
  (((uint32)(v) << 0U) & FM_PCR8_TXSEL)
#define GFV_PCR8_TXSEL(v) \
  (((uint32)(v) & FM_PCR8_TXSEL) >> 0U)

#define UART_PCR9_OFF  0xa4U

#define FM_PCR9_RXFILTCTL  ((uint32)0x7U << 18U)
#define FV_PCR9_RXFILTCTL(v) \
  (((uint32)(v) << 18U) & FM_PCR9_RXFILTCTL)
#define GFV_PCR9_RXFILTCTL(v) \
  (((uint32)(v) & FM_PCR9_RXFILTCTL) >> 18U)

#define BM_PCR9_RXSYNCEN  ((uint32)0x01U << 17U)

#define BM_PCR9_RXPOL  ((uint32)0x01U << 16U)

#define FM_PCR9_RXEDGESEL  ((uint32)0x3U << 14U)
#define FV_PCR9_RXEDGESEL(v) \
  (((uint32)(v) << 14U) & FM_PCR9_RXEDGESEL)
#define GFV_PCR9_RXEDGESEL(v) \
  (((uint32)(v) & FM_PCR9_RXEDGESEL) >> 14U)

#define FM_PCR9_RXMODE  ((uint32)0x3U << 12U)
#define FV_PCR9_RXMODE(v) \
  (((uint32)(v) << 12U) & FM_PCR9_RXMODE)
#define GFV_PCR9_RXMODE(v) \
  (((uint32)(v) & FM_PCR9_RXMODE) >> 12U)

#define FM_PCR9_RXSEL  ((uint32)0xfU << 8U)
#define FV_PCR9_RXSEL(v) \
  (((uint32)(v) << 8U) & FM_PCR9_RXSEL)
#define GFV_PCR9_RXSEL(v) \
  (((uint32)(v) & FM_PCR9_RXSEL) >> 8U)

#define BM_PCR9_TXPOL  ((uint32)0x01U << 7U)

#define FM_PCR9_TXMODE  ((uint32)0x7U << 4U)
#define FV_PCR9_TXMODE(v) \
  (((uint32)(v) << 4U) & FM_PCR9_TXMODE)
#define GFV_PCR9_TXMODE(v) \
  (((uint32)(v) & FM_PCR9_TXMODE) >> 4U)

#define FM_PCR9_TXSEL  ((uint32)0xfU << 0U)
#define FV_PCR9_TXSEL(v) \
  (((uint32)(v) << 0U) & FM_PCR9_TXSEL)
#define GFV_PCR9_TXSEL(v) \
  (((uint32)(v) & FM_PCR9_TXSEL) >> 0U)

#define UART_PCR10_OFF  0xa8U

#define FM_PCR10_RXFILTCTL  ((uint32)0x7U << 18U)
#define FV_PCR10_RXFILTCTL(v) \
  (((uint32)(v) << 18U) & FM_PCR10_RXFILTCTL)
#define GFV_PCR10_RXFILTCTL(v) \
  (((uint32)(v) & FM_PCR10_RXFILTCTL) >> 18U)

#define BM_PCR10_RXSYNCEN  ((uint32)0x01U << 17U)

#define BM_PCR10_RXPOL  ((uint32)0x01U << 16U)

#define FM_PCR10_RXEDGESEL  ((uint32)0x3U << 14U)
#define FV_PCR10_RXEDGESEL(v) \
  (((uint32)(v) << 14U) & FM_PCR10_RXEDGESEL)
#define GFV_PCR10_RXEDGESEL(v) \
  (((uint32)(v) & FM_PCR10_RXEDGESEL) >> 14U)

#define FM_PCR10_RXMODE  ((uint32)0x3U << 12U)
#define FV_PCR10_RXMODE(v) \
  (((uint32)(v) << 12U) & FM_PCR10_RXMODE)
#define GFV_PCR10_RXMODE(v) \
  (((uint32)(v) & FM_PCR10_RXMODE) >> 12U)

#define FM_PCR10_RXSEL  ((uint32)0xfU << 8U)
#define FV_PCR10_RXSEL(v) \
  (((uint32)(v) << 8U) & FM_PCR10_RXSEL)
#define GFV_PCR10_RXSEL(v) \
  (((uint32)(v) & FM_PCR10_RXSEL) >> 8U)

#define BM_PCR10_TXPOL  ((uint32)0x01U << 7U)

#define FM_PCR10_TXMODE  ((uint32)0x7U << 4U)
#define FV_PCR10_TXMODE(v) \
  (((uint32)(v) << 4U) & FM_PCR10_TXMODE)
#define GFV_PCR10_TXMODE(v) \
  (((uint32)(v) & FM_PCR10_TXMODE) >> 4U)

#define FM_PCR10_TXSEL  ((uint32)0xfU << 0U)
#define FV_PCR10_TXSEL(v) \
  (((uint32)(v) << 0U) & FM_PCR10_TXSEL)
#define GFV_PCR10_TXSEL(v) \
  (((uint32)(v) & FM_PCR10_TXSEL) >> 0U)

#define UART_PCR11_OFF  0xacU

#define FM_PCR11_RXFILTCTL  ((uint32)0x7U << 18U)
#define FV_PCR11_RXFILTCTL(v) \
  (((uint32)(v) << 18U) & FM_PCR11_RXFILTCTL)
#define GFV_PCR11_RXFILTCTL(v) \
  (((uint32)(v) & FM_PCR11_RXFILTCTL) >> 18U)

#define BM_PCR11_RXSYNCEN  ((uint32)0x01U << 17U)

#define BM_PCR11_RXPOL  ((uint32)0x01U << 16U)

#define FM_PCR11_RXEDGESEL  ((uint32)0x3U << 14U)
#define FV_PCR11_RXEDGESEL(v) \
  (((uint32)(v) << 14U) & FM_PCR11_RXEDGESEL)
#define GFV_PCR11_RXEDGESEL(v) \
  (((uint32)(v) & FM_PCR11_RXEDGESEL) >> 14U)

#define FM_PCR11_RXMODE  ((uint32)0x3U << 12U)
#define FV_PCR11_RXMODE(v) \
  (((uint32)(v) << 12U) & FM_PCR11_RXMODE)
#define GFV_PCR11_RXMODE(v) \
  (((uint32)(v) & FM_PCR11_RXMODE) >> 12U)

#define FM_PCR11_RXSEL  ((uint32)0xfU << 8U)
#define FV_PCR11_RXSEL(v) \
  (((uint32)(v) << 8U) & FM_PCR11_RXSEL)
#define GFV_PCR11_RXSEL(v) \
  (((uint32)(v) & FM_PCR11_RXSEL) >> 8U)

#define BM_PCR11_TXPOL  ((uint32)0x01U << 7U)

#define FM_PCR11_TXMODE  ((uint32)0x7U << 4U)
#define FV_PCR11_TXMODE(v) \
  (((uint32)(v) << 4U) & FM_PCR11_TXMODE)
#define GFV_PCR11_TXMODE(v) \
  (((uint32)(v) & FM_PCR11_TXMODE) >> 4U)

#define FM_PCR11_TXSEL  ((uint32)0xfU << 0U)
#define FV_PCR11_TXSEL(v) \
  (((uint32)(v) << 0U) & FM_PCR11_TXSEL)
#define GFV_PCR11_TXSEL(v) \
  (((uint32)(v) & FM_PCR11_TXSEL) >> 0U)

#define UART_PCR12_OFF  0xb0U

#define FM_PCR12_BDRERR_UL  ((uint32)0x7U << 9U)
#define FV_PCR12_BDRERR_UL(v) \
  (((uint32)(v) << 9U) & FM_PCR12_BDRERR_UL)
#define GFV_PCR12_BDRERR_UL(v) \
  (((uint32)(v) & FM_PCR12_BDRERR_UL) >> 9U)

#define FM_PCR12_BDRERR_DL  ((uint32)0x7U << 6U)
#define FV_PCR12_BDRERR_DL(v) \
  (((uint32)(v) << 6U) & FM_PCR12_BDRERR_DL)
#define GFV_PCR12_BDRERR_DL(v) \
  (((uint32)(v) & FM_PCR12_BDRERR_DL) >> 6U)

#define FM_PCR12_CTL  ((uint32)0x3fU << 0U)
#define FV_PCR12_CTL(v) \
  (((uint32)(v) << 0U) & FM_PCR12_CTL)
#define GFV_PCR12_CTL(v) \
  (((uint32)(v) & FM_PCR12_CTL) >> 0U)

#define UART_PCR13_OFF  0xb4U

#define BM_PCR13_LIN_LOOP_INT_OPT  ((uint32)0x01U << 11U)

#define BM_PCR13_OPT_SLCH_EN  ((uint32)0x01U << 10U)

#define BM_PCR13_OPT_SHCL_EN  ((uint32)0x01U << 9U)

#define BM_PCR13_BUS_INJ_EN  ((uint32)0x01U << 8U)

#define FM_PCR13_BUS_INJ_NUM  ((uint32)0xffU << 0U)
#define FV_PCR13_BUS_INJ_NUM(v) \
  (((uint32)(v) << 0U) & FM_PCR13_BUS_INJ_NUM)
#define GFV_PCR13_BUS_INJ_NUM(v) \
  (((uint32)(v) & FM_PCR13_BUS_INJ_NUM) >> 0U)

#define UART_REG_PARITY_ERR_INT_STAT_OFF  0xe0U

#define BM_REG_PARITY_ERR_INT_STAT_REG_PARITY_ERR  ((uint32)0x01U << 0U)

#define UART_REG_PARITY_ERR_INT_STAT_EN_OFF  0xe4U

#define BM_REG_PARITY_ERR_INT_STAT_EN_REG_PARITY_ERR  ((uint32)0x01U << 0U)

#define UART_REG_PARITY_ERR_INT_SIG_EN_OFF  0xe8U

#define BM_REG_PARITY_ERR_INT_SIG_EN_REG_PARITY_ERR  ((uint32)0x01U << 0U)

#define UART_PSR0_OFF  0x100U

#define FM_PSR0_LIN_CHECKSUM  ((uint32)0xffU << 24U)
#define FV_PSR0_LIN_CHECKSUM(v) \
  (((uint32)(v) << 24U) & FM_PSR0_LIN_CHECKSUM)
#define GFV_PSR0_LIN_CHECKSUM(v) \
  (((uint32)(v) & FM_PSR0_LIN_CHECKSUM) >> 24U)

#define FM_PSR0_PCMD_STATE  ((uint32)0x3U << 22U)
#define FV_PSR0_PCMD_STATE(v) \
  (((uint32)(v) << 22U) & FM_PSR0_PCMD_STATE)
#define GFV_PSR0_PCMD_STATE(v) \
  (((uint32)(v) & FM_PSR0_PCMD_STATE) >> 22U)

#define BM_PSR0_MUTEMODE  ((uint32)0x01U << 21U)

#define FM_PSR0_ABR_STATE  ((uint32)0x7U << 18U)
#define FV_PSR0_ABR_STATE(v) \
  (((uint32)(v) << 18U) & FM_PSR0_ABR_STATE)
#define GFV_PSR0_ABR_STATE(v) \
  (((uint32)(v) & FM_PSR0_ABR_STATE) >> 18U)

#define FM_PSR0_RXBREAK_STATE  ((uint32)0x3U << 16U)
#define FV_PSR0_RXBREAK_STATE(v) \
  (((uint32)(v) << 16U) & FM_PSR0_RXBREAK_STATE)
#define GFV_PSR0_RXBREAK_STATE(v) \
  (((uint32)(v) & FM_PSR0_RXBREAK_STATE) >> 16U)

#define FM_PSR0_IOTX_STATE  ((uint32)0xfU << 12U)
#define FV_PSR0_IOTX_STATE(v) \
  (((uint32)(v) << 12U) & FM_PSR0_IOTX_STATE)
#define GFV_PSR0_IOTX_STATE(v) \
  (((uint32)(v) & FM_PSR0_IOTX_STATE) >> 12U)

#define FM_PSR0_IORX_STATE  ((uint32)0xfU << 8U)
#define FV_PSR0_IORX_STATE(v) \
  (((uint32)(v) << 8U) & FM_PSR0_IORX_STATE)
#define GFV_PSR0_IORX_STATE(v) \
  (((uint32)(v) & FM_PSR0_IORX_STATE) >> 8U)

#define FM_PSR0_LIN_STATE  ((uint32)0xfU << 4U)
#define FV_PSR0_LIN_STATE(v) \
  (((uint32)(v) << 4U) & FM_PSR0_LIN_STATE)
#define GFV_PSR0_LIN_STATE(v) \
  (((uint32)(v) & FM_PSR0_LIN_STATE) >> 4U)

#define FM_PSR0_FC_STATE  ((uint32)0x7U << 0U)
#define FV_PSR0_FC_STATE(v) \
  (((uint32)(v) << 0U) & FM_PSR0_FC_STATE)
#define GFV_PSR0_FC_STATE(v) \
  (((uint32)(v) & FM_PSR0_FC_STATE) >> 0U)

#define UART_PSR1_OFF  0x104U

#define FM_PSR1_ABRCHAR  ((uint32)0xffU << 24U)
#define FV_PSR1_ABRCHAR(v) \
  (((uint32)(v) << 24U) & FM_PSR1_ABRCHAR)
#define GFV_PSR1_ABRCHAR(v) \
  (((uint32)(v) & FM_PSR1_ABRCHAR) >> 24U)

#define FM_PSR1_AUTOBAUDRATE  ((uint32)0xffffffU << 0U)
#define FV_PSR1_AUTOBAUDRATE(v) \
  (((uint32)(v) << 0U) & FM_PSR1_AUTOBAUDRATE)
#define GFV_PSR1_AUTOBAUDRATE(v) \
  (((uint32)(v) & FM_PSR1_AUTOBAUDRATE) >> 0U)

#define UART_PSR2_OFF  0x108U

#define FM_PSR2_ABR_LOW  ((uint32)0x3ffffffU << 0U)
#define FV_PSR2_ABR_LOW(v) \
  (((uint32)(v) << 0U) & FM_PSR2_ABR_LOW)
#define GFV_PSR2_ABR_LOW(v) \
  (((uint32)(v) & FM_PSR2_ABR_LOW) >> 0U)

#define UART_PSR3_OFF  0x10cU

#define FM_PSR3_ABR_HIGH  ((uint32)0x3ffffffU << 0U)
#define FV_PSR3_ABR_HIGH(v) \
  (((uint32)(v) << 0U) & FM_PSR3_ABR_HIGH)
#define GFV_PSR3_ABR_HIGH(v) \
  (((uint32)(v) & FM_PSR3_ABR_HIGH) >> 0U)

#define UART_PSR4_OFF  0x110U

#define FM_PSR4_LIN_BUS_CHECKSUM  ((uint32)0xffU << 24U)
#define FV_PSR4_LIN_BUS_CHECKSUM(v) \
  (((uint32)(v) << 24U) & FM_PSR4_LIN_BUS_CHECKSUM)
#define GFV_PSR4_LIN_BUS_CHECKSUM(v) \
  (((uint32)(v) & FM_PSR4_LIN_BUS_CHECKSUM) >> 24U)

#define FM_PSR4_LINPID  ((uint32)0xffU << 0U)
#define FV_PSR4_LINPID(v) \
  (((uint32)(v) << 0U) & FM_PSR4_LINPID)
#define GFV_PSR4_LINPID(v) \
  (((uint32)(v) & FM_PSR4_LINPID) >> 0U)

#define UART_PSR5_OFF  0x114U

#define UART_PSR6_OFF  0x118U

#define UART_PSR7_OFF  0x11cU

#define UART_TXDR_OFF  0x200U

#define UART_RXDR_OFF  0x300U

#ifdef __cplusplus
}
#endif

#endif   /* UART_IP_REG_H */
